High-Speed Packet Processing using Reconfigurable Computing

@article{Brebner2014HighSpeedPP,
  title={High-Speed Packet Processing using Reconfigurable Computing},
  author={Gordon J. Brebner and Weirong Jiang},
  journal={IEEE Micro},
  year={2014},
  volume={34},
  pages={8-18}
}
Internet applications, notably streaming video, demand extremely high communication speeds in core networks, currently 100 Gbps and moving toward 400 Gbps and beyond. Data packets must be processed at these rates, presenting serious challenges for traditional computing approaches. This article presents a tool chain that maps a domain-specific packet-processing language called PX to high-performance reconfigurable-computing architectures based on field-programmable gate array (FPGA) technology… CONTINUE READING
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