• Corpus ID: 12000553

High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells

@article{Mirzaee2010HighSN,
  title={High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells},
  author={Reza Faghih Mirzaee and Mohammad Hossein Moaiyeri and Keivan Navi},
  journal={International Journal of Electrical and Computer Engineering},
  year={2010},
  volume={4},
  pages={531-537}
}
In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18 m CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around… 

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