• Corpus ID: 14450686

High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based On Ancient Indian Vedic Mathematics

@inproceedings{Thapliyal2004HighSE,
  title={High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based On Ancient Indian Vedic Mathematics},
  author={Himanshu Thapliyal and M. B. Srinivas},
  year={2004}
}

• H. Thapliyal, M. Srinivas
• Published 2004
• Computer Science

A N X N bit parallel overlay multiplier architecture is designed for high speed DSP operations. The architecture is based on the vertical and crosswise algorithm of ancient Indian Vedic Mathematics. In the proposed architecture grouping of the bits 4 at a time is done for both the multiplicand and multiplier. Thus the whole multiplication operation is decomposed into 4x4 bit multiplication modules. The 4x4 multiplication modules can be implemented by using any multiplier such as array, booth, wallace or future proposed efficient multiplier. It has been demonstrated that implementing the array and booth multiplier as 4x4 modules in the proposed architecture leads to a considerable improvement in their efficiency. Due to its efficient performance, the overlay architecture is a boon for DSP applications such as multimedia and image processing. In order to test the effect of further decomposition of the bits on the efficiency of the architecture, the 4x4 multiply module are further decomposed into parallel 2x2 multiply modules by grouping two bits at a time for both 4 bit multiplicand and multiplier. The results has shown that decomposition nearly reaches a saturation level in its efficiency at 4x4 decomposition and further decomposition has a not a significant improvement in the architecture efficiency .