# High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based On Ancient Indian Vedic Mathematics

@inproceedings{Thapliyal2004HighSE, title={High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based On Ancient Indian Vedic Mathematics}, author={Himanshu Thapliyal and M. B. Srinivas}, year={2004} }

A N X N bit parallel overlay multiplier architecture is designed for high speed DSP operations. The architecture is based on the vertical and crosswise algorithm of ancient Indian Vedic Mathematics. In the proposed architecture grouping of the bits 4 at a time is done for both the multiplicand and multiplier. Thus the whole multiplication operation is decomposed into 4x4 bit multiplication modules. The 4x4 multiplication modules can be implemented by using any multiplier such as array, booth…

## 117 Citations

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In this paper, general technique for NxN multiplication is proposed and implemented; this gives less delay for calculating the multiplication results for 8x8 Bit Vedic Multiplier.

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### Design and FPGA implementation of optimized 32-bit Vedic multiplier and square architectures

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This paper presents a high speed 8x8 bit Vedic multiplier architecture which is quite different from the Conventional method of multiplication like add and shift and is based on Vertical and Crosswise structure of Ancient Indian Vedic Mathematics.

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A novel architecture to perform high speed multiplication using ancient Vedic maths techniques and a new high speed approach utilizing 4:2 compressors and novel 7:2 compressor for addition has been incorporated in the same and has been explored.

### ALU Using Area Optimized Vedic Multiplier

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In the work it is further optimized the Vedic multiplier type Urdhva Triyakbhyam by replacing the traditional adder with Carry save Adder to have more Delay Optimization and shows improvement of speed as compare with the traditional designs.

### Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System

- Computer Science2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)
- 2018

A high-speed Vedic multiplier based on the Urdhva Tiryagbhyam sutra of Vedic mathematics that incorporates a novel adder based on Quaternary Signed digit number system that shows a maximum of 88.75% speed improvement with respect to Multi Value logic based 128x128 Vedic multipliers.

### A low power decomposed hierarchical multiplier architecture embedding multiplexer based full adders

- Computer Science48th Midwest Symposium on Circuits and Systems, 2005.
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This paper proposes a novel 4times4 multiplier architecture which is efficient in terms of power without a significant increase in delay and area, especially designed for partition multipliers having…

### A Reduced-Bit Multiplication Algorithm for Digital Arithmetic

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A reduced-bit multiplication algorithm based on the ancient Vedic multiplication formulae, Urdhva tiryakbhyam and Nikhilam, is proposed and is further optimized by use of some general arithmetic operations such as expansion and bit-shifting to take advantage of bit-reduction in multiplication.

### Design of Multiply and Accumulate Unit using Vedic Multiplication Techniques

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The results show that design of MAC unit using Vedic multiplica- tion is efficient in terms of area/speed compared to conventional multiplication.

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