High Speed, Low Power Design Rules for SRAM Precharge and Self-timing under Technology Variations

Abstract

Due to low-power and reliability requirements, supply voltage is constantly decreasing. On the other hand, high speed operation is required along with increasing memory size. In a CMOS SRAM, power can be saved and cycle time reduced if bit lines are not precharged to VDD. The aim of this work is to analytically derive a model for the design of precharge and… (More)

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