High Performance and Low Power VLSI Synchronous Systems Using an Explicit Pulsed Dual Edge Triggered Flip Flops

Abstract

An explicit pulsed dual edge triggered sense amplifier flip flops (DET-FF).In this dual edge triggered sense amplifier flip flop is used for low–power consumption and high performance application. By incorporating the dual edge triggering mechanism, the dual edge triggered flip flop is able to achieve low power consumption that has minimum delay. Clock… (More)

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Cite this paper

@inproceedings{Ramya2014HighPA, title={High Performance and Low Power VLSI Synchronous Systems Using an Explicit Pulsed Dual Edge Triggered Flip Flops}, author={R. Ramya and V. Saranya and Y. Vivekananth}, year={2014} }