High Performance Single-Chip FPGA Rijndael Algorithm Implementations

@inproceedings{ONeill2001HighPS,
  title={High Performance Single-Chip FPGA Rijndael Algorithm Implementations},
  author={M{\'a}ire O'Neill and John V. McCanny},
  booktitle={CHES},
  year={2001}
}
This paper describes high performance single-chip FPGA implementations of the new Advanced Encryption Standard (AES) algorithm, Rijndael. The designs are implemented on the Virtex-E FPGA family of devices. FPGAs have proven to be very effective in implementing encryption algorithms. They provide more flexibility than ASIC implementations and produce higher data-rates than equivalent software implementations. A novel, generic, parameterisable Rijndael encryptor core capable of supporting varying… 
Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm
TLDR
The FPGA implementation described here is that of a fully pipelined single-chip Rijndael design which runs at a data rate of 7 Gbits/sec on a Xilinx Virtex-E XCV812E-8-BG560 FPGAs device, which proves to be one of the fastest single- chip RIJndael implementations currently available.
Rijndael FPGA Implementations Utilising Look-Up Tables
TLDR
A Look-Up Table (LUT) methodology is introduced where complex and slow operations are replaced by simple LUTs in single-chip FPGA Rijndael algorithm implementations of the Advanced Encryption Standard (AES).
Single-chip FPGA implementation of a pipelined, memory-based AES Rijndael encryption design
  • K. Stevens, O. Mohamed
  • Computer Science
    Canadian Conference on Electrical and Computer Engineering, 2005.
  • 2005
TLDR
A fully synchronous, memory-based, single-chip FPGA implementation of the recent AES standard, Rijndael encryption algorithm, which encrypts the necessary AES rounds in an arithmetic pipeline structure that targets a Xilinx VirtexIIPro device.
Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications
TLDR
This work purpose an efficient solution to combine Rijndael encryption and decryption in one FPGA design, with a strong focus on low area constraints, which fits into the smallest Xilinx FPGAs, deals with data streams of 208 Mbps, and improves by 68% the best-known similar designs in terms of ratio Throughput/Area.
Utilizing hard cores of modern FPGA devices for high-performance cryptography
  • T. Güneysu
  • Computer Science, Mathematics
    Journal of Cryptographic Engineering
  • 2011
TLDR
This article presents a unique design approach for the implementation of standardized symmetric and asymmetric cryptosystems on modern FPGA devices that enable a performance for the symmetric AES block cipher and a throughput of more than 30.000 scalar multiplications per second for asymmetric Elliptic Curve Cryptography over NIST’s P-224 prime.
PERFORMANCE ANALYSIS OF CRYPTOGRAPHIC VLSI DATA
TLDR
An optimized coding for the implementation of Rijndael algorithm for 256 bytes has been developed and the speed factor of the algorithm implementation has been targeted and a software code in verilog which boasts of a throughput of 2.18 Gb/sec have been developed.
A system level implementation of Rijndael on a memory-slot based FPGA card
TLDR
This paper describes system level issues encountered in a high performance implementation of a Rijndael encryption core on a memory-slot based reconfigurable computing platform called Pilchard and shows that for the design presented, the highest performance was achieved by implementing a core with a single round.
Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA
This paper describes a high performance single-chip FPGA implementation of the new Advanced Encryption Standard (AES) algorithm dealing with 128-bit data/key blocks and operating in Counter (CTR)
AES Encryption Algorithm Hardware Implementation Architecture: Resource and Execution Time Optimization
TLDR
An architecture to implement Advanced Encryption Standard (AES) Rijndael algorithm in reconfigurable hardware in FPGA that can be used in a wide range of embedded applications is presented and compared with other reference implementations.
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