High-Performance Hardware Architectures for Galois Counter Mode

@article{Satoh2009HighPerformanceHA,
  title={High-Performance Hardware Architectures for Galois Counter Mode},
  author={Akashi Satoh and Takeshi Sugawara and Takafumi Aoki},
  journal={IEEE Transactions on Computers},
  year={2009},
  volume={58},
  pages={917-930}
}
Various high-performance hardware architectures for Galois counter mode (GCM) in conjunction with various advanced encryption standard (AES) circuits and multiplier-adders are proposed. A total of 17 GCM-AES circuits were synthesized by using a 130-nm CMOS standard cell library, and the trade-offs between speed and hardware resources were evaluated. Our flexible architectures achieved a wide variety of performances from compact (2.56 Gbps with 34.5 Kgates) to high speed (62.6 Gbps with 979.3… CONTINUE READING
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