High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability

@article{Wang2009HighLevelTS,
  title={High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability},
  author={Sying-Jyan Wang and Tung-Hua Yeh},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2009},
  volume={28},
  pages={1583-1596}
}
A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay-fault coverage is usually attributed to the fact that a two-pattern test for delay testing cannot be delivered to modules under test in two… CONTINUE READING

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