High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective

  title={High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective},
  author={Srivaths Ravi and Michael Joseph},
  journal={ACM Trans. Design Autom. Electr. Syst.},
High-level test synthesis is a special class of high-level synthesis having testability as one of the important components. This article presents a detailed survey on recent developments in high-level test synthesis from a synthesis process flow perspective. It also presents a survey on controller synthesis techniques for testability. 

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