High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

@article{Curreri2011HighLevelSO,
  title={High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis},
  author={John Curreri and Greg Stitt and Alan D. George},
  journal={Int. J. Reconfig. Comp.},
  year={2011},
  volume={2011},
  pages={406857:1-406857:17}
}
Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy registertransfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques… CONTINUE READING
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