High-Level Synthesis Challenges and Solutions for a Dynamically Reconfigurable Processor

Abstract

A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone finite state machine and that switches "contexts" consisting of many operational and storage units in processing elements (PEs) and wires between them. Utilizing the resources not… (More)
DOI: 10.1145/1233501.1233647

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