High Level RTOS Scheduler Modeling for a Fast Design Validation

Abstract

The use of higher level specification models will open new sceneries for optimization and architecture exploration like CPU/RTOS tradeoffs. Scheduling decision for realtime embedded applications has a great impact on system performance and, therefore, it is an important issue in RTOS design. Moreover, it is highly desirable to have the system designer able to evaluate and select the right scheduling policy at high abstraction levels, in order to allow faster exploration of the design space. In this paper, we address this problem by introducing an abstract RTOS scheduling model as well as a new approach to refine an unscheduled high level model to a high level model with RTOS scheduling. This approach is built on the top of the standard SystemC kernel and enables the system designer to quickly evaluate different scheduling policies and make the best choice in early design stages. Furthermore, we present a case study where our model is used to simulate and analyze a telecom system

DOI: 10.1109/ISVLSI.2007.49

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Cite this paper

@article{Hessel2007HighLR, title={High Level RTOS Scheduler Modeling for a Fast Design Validation}, author={Fabiano Hessel and C{\'e}sar A. M. Marcon and Tatiana Gadelha Serra dos Santos}, journal={IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)}, year={2007}, pages={461-466} }