High Level Modeling and Simulation of a Baseband Processor for the 60 GHz Band


This paper describes the high level behavioral model of a baseband processor to be implemented in FPGA devices. The final target is a reconfigurable transceiver for different technologies in the 60 GHz. For now, we implement the complete model of the AV mode of IEEE 802.15.3c. Simulations with the Matlab/Simulink model permitted to determine the adequate… (More)
DOI: 10.1109/DSD.2012.72

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