High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems


This poster presents the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied in the perspective of making easier and more practical the design of future GALS or GALA SoCs. This workfocuses on high-Ievel modeling and delayinsensitive implementations of low-power and… (More)


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