High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation

@article{Sung2006HighEfficiencyAL,
  title={High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation},
  author={Tze-Yun Sung and Yaw-Shih Shieh and Chun-Wang Yu and Hsi-Chin Hsin},
  journal={2006 Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06)},
  year={2006},
  pages={191-196}
}
Two dimensional discrete cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems. In this paper, efficient architectures with parallel and pipelined structures are proposed to implement 8times8 DCT and IDCT processors. In which, two 8-point DCT/IDCT processors with dual-bank of SRAM (128 words) and coefficient ROM (6 words), two multiplexers, and control unit are involved. The kernel arithmetic unit (AU) is designed by using CORDIC arithmetic. The… CONTINUE READING
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