High Efficiency Synchronous DRAM Controller for H.264 HDTV Encoder


A high efficiency memory controller of Synchronous DRAM is proposed to improve memory bandwidth in H.264 HDTV encoder. The feature of SDRAM and memory access pattern of H. 264/AVC encoder is analyzed for suitable controller architecture designing. A new data arrangement in SDRAM has been used to improve bus efficiency by reducing the overhead cycle of page… (More)
DOI: 10.1109/SIPS.2007.4387575


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