High Efficiency Generalized Parallel Counters for Xilinx FPGAs

@article{Khurshid2015HighEG,
  title={High Efficiency Generalized Parallel Counters for Xilinx FPGAs},
  author={Burhan Khurshid and Roohie Naaz Mir},
  journal={2015 IEEE 22nd International Conference on High Performance Computing (HiPC)},
  year={2015},
  pages={40-46}
}
Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Prior work on GPC synthesis using FPGAs has focused on utilizing the fast carry chain and mapping the logic onto LUTs. This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. Modern day Xilinx FPGAs support 6-input LUTs that can be used in the dual mode for achieving high logic density. In this work we present a heuristic that… CONTINUE READING