High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

@article{Chiang2006HighDensityRL,
  title={High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices},
  author={Meng-Hsueh Chiang and Keunwoo Kim and C. Chuang and C. Tretz},
  journal={IEEE Transactions on Electron Devices},
  year={2006},
  volume={53},
  pages={2370-2377}
}
Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The… CONTINUE READING
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