High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

  title={High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices},
  author={Meng-Hsueh Chiang and Keunwoo Kim and C. Chuang and C. Tretz},
  journal={IEEE Transactions on Electron Devices},
Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The… CONTINUE READING
Highly Cited
This paper has 68 citations. REVIEW CITATIONS
46 Citations
16 References
Similar Papers


Publications citing this paper.
Showing 1-10 of 46 extracted citations

69 Citations

Citations per Year
Semantic Scholar estimates that this publication has 69 citations based on the available data.

See our FAQ for additional information.


Publications referenced by this paper.
Showing 1-10 of 16 references

Device scaling limits of Si MOSFETs and their application dependencies

  • D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, H.-S.P. Wong
  • Proc. IEEE, vol. 89, no. 3, pp. 259–288, Mar…
  • 2001
Highly Influential
9 Excerpts

Fundamentals of Modern VLSI Devices

  • Y. Taur, T. Ning
  • 1998
Highly Influential
5 Excerpts

A high threshold voltage-controllable 4T FinFET with an CHIANG et al.: REDUCED-STACK LOGIC CIRCUIT TECHNIQUES USING GATE CONTROLLED DG DEVICES 2377 8.5-nm-thick Si-Fin channel

  • Y. Liu, M. Masahara, +4 authors E. Suzuki
  • IEEE Electron Device Lett., vol. 25, no. 7, pp…
  • 2004
1 Excerpt

Similar Papers

Loading similar papers…