Hierarchies for the Modeling and Verification of Embedded Systems

Abstract

A flat representation of a realistic embedded system can be too big and complex to handle and understand. In order to represent efficiently large systems, a mechanism for hierarchical composition is needed so that the model may be constructed in a structured manner and composed of simpler units easily comprehensible by the designer at each description level. In this report we formally define the notion of hierarchy for a Petri net based representation used for modeling embedded systems. We show how small parts of a large system may be transformed by using the concept of hierarchy as well as the advantages of a transformational approach in the verification of embedded systems. A real-life example illustrates the feasibility of our approach on practical applications. This work has been done in the frame of the SAVE project, which aims to study the specification and verification of heterogeneous electronic systems.

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Cite this paper

@inproceedings{Corts2001HierarchiesFT, title={Hierarchies for the Modeling and Verification of Embedded Systems}, author={Luis Alejandro Cort{\'e}s and Petru Eles and Zebo Peng}, year={2001} }