Hierarchical verification of chip-level ESD design rules

@article{Lu2010HierarchicalVO,
  title={Hierarchical verification of chip-level ESD design rules},
  author={Ziyang Lu and David Averill Bell},
  journal={Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010},
  year={2010},
  pages={1-6}
}
Verification of net-oriented ESD rules is rapidly becoming critical for nanometer design. To meet chip-level complexity and size challenges, a novel approach using topology-aware net types is developed to enable fast, hierarchical verification. This is applied to ESD design rules for power/ground interfaces and successfully adopted in production verification flows. 
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