Hierarchical routing architectures in clustered 2D-mesh Networks-on-Chip

@article{Winter2010HierarchicalRA,
  title={Hierarchical routing architectures in clustered 2D-mesh Networks-on-Chip},
  author={Markus Winter and Steffen Prusseit and P. Fettweis Gerhard},
  journal={2010 International SoC Design Conference},
  year={2010},
  pages={388-391}
}
The growing size of Multi-Processor Systems-on-Chip (MP-SoC) calls for Networks-on-Chip (NoC) which scale with the increasing number of modules attached to them. Though current, 2D-mesh based NoCs scale linearly with the number of modules attached to them, their performance in terms of achievable throughput under typical traffic scenarios degrades. Clustered, hierarchical 2D-mesh NoCs may provide a solution to this problem by shortening the distance between two modules and adding more bandwidth… CONTINUE READING
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