Hierarchical Random Simulation Approach For The Verification Of S/390 Cmos Multiprocessors

@article{Walter1997HierarchicalRS,
  title={Hierarchical Random Simulation Approach For The Verification Of S/390 Cmos Multiprocessors},
  author={Jan Walter and Jentje Leenstra and G. Dottling and Bernd Leppla and H. Munster and Klaus Werner Kark and Bruce Wile},
  journal={Proceedings of the 34th Design Automation Conference},
  year={1997},
  pages={89-94}
}
In this paper an approach is presented for the hierarchical verification of the memory control units, I/O adapters and processor interconnect units as found in multiprocessor computer systems. It is shown how such units could be verified better and faster by the introduction of random executable timing diagrams and associated CAD tool support. Furthermore, it is shown how the timing diagrams for the unit network verification are easily derived from the timing diagrams specified for the units… CONTINUE READING

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Publications referenced by this paper.
SHOWING 1-2 OF 2 REFERENCES

AVPCEN-A Test Generator,for Architecture Verifkarion

A. Chandra et. al
  • IEEE Trans. OD Very Large Scale htegration (VLSt) Systems,
  • 1995

Test Program Generation,for Functional Verlfication ofPowerPC Processors i n IBM

A. Aharon et. al
  • Proceedings 32th ACM/ IEEE Design Automation Conference,
  • 1995