Hierarchical Global Wiring for Custom Chip Design


We present a global wiring algorithm used in a top-down physical design environment, i.e. macros are laid out only after global wiring is done, and wires are allowed to pass through macros (wiring-through model). The floorplan of the chip is in the form of a slicing structure. The algorithm is based on a hierarchical scheme. The final result is obtained… (More)


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@article{Luk1986HierarchicalGW, title={Hierarchical Global Wiring for Custom Chip Design}, author={W. K. Luk and D. Tang and C. K. Wong}, journal={23rd ACM/IEEE Design Automation Conference}, year={1986}, pages={481-489} }