Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation

Abstract

We present a routability-driven top-down clustering technique for area and power reduction in clustered FPGAs. This technique is based on a multilevel partitioning approach. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 15% is achieved over previously published results. Power dissipation is reduced by an average of 8.5%

DOI: 10.1109/RECONFIG.2005.23

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