Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors

  title={Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors},
  author={Sanghyun Park and Aviral Shrivastava and Yunheung Paek},
  journal={2008 Design, Automation and Test in Europe},
The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-end processors can use elaborate techniques like multiple issue, out-of-order execution, speculative execution, value prediction etc. to tolerate high memory latencies, they are often not viable solutions for embedded processors, due to significant area, power and chip complexity overheads. This paper proposes a hardware… CONTINUE READING
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