Heat-removal performance scaling of interlayer cooled chip stacks

@article{Brunschwiler2010HeatremovalPS,
  title={Heat-removal performance scaling of interlayer cooled chip stacks},
  author={Thomas Brunschwiler and Stephan Paredes and Ute Drechsler and Bruno Michel and W. Cesar and Yusuf Leblebici and Bernhard Wunderle and Herbert Reichl},
  journal={2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems},
  year={2010},
  pages={1-12}
}
Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1cm2. The implementation of 100µm pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature increase of 54.7K at 1bar pressure drop with water as coolant for 250W/cm2 hot-spot and 50W/cm2… CONTINUE READING
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