Heads and tails: a variable-length instruction format supporting parallel fetch and decode

@inproceedings{Pan2001HeadsAT,
  title={Heads and tails: a variable-length instruction format supporting parallel fetch and decode},
  author={Heidi Pan and Krste Asanovic},
  booktitle={CASES},
  year={2001}
}
Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and decode. This paper presents a new variable-length instruction format that supports parallel fetch and decode of multiple instructions per cycle, allowing both high code density and rapid execution for high-performance embedded processors. In contrast to earlier schemes that store compressed variable-length instructions in main… CONTINUE READING
Highly Cited
This paper has 26 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 17 extracted citations

References

Publications referenced by this paper.
Showing 1-5 of 5 references

Kissell. MIPS16: High-density MIPS for the embedded market

  • D. Kevin
  • In Proceedings RTS97,
  • 1997
Highly Influential
5 Excerpts

MIPS RISC Architecture (R2000/R3000)

  • G. Kane
  • Prentice Hall,
  • 1989
Highly Influential
6 Excerpts

Similar Papers

Loading similar papers…