• Corpus ID: 253498982

Hardware optimized parity check gates for superconducting surface codes

@inproceedings{Reagor2022HardwareOP,
  title={Hardware optimized parity check gates for superconducting surface codes},
  author={Matthew Reagor and Thomas C. Bohdanowicz. David Rodriguez Perez and Eyob A. Sete and William J. Zeng},
  year={2022}
}
Error correcting codes use multi-qubit measurements to realize fault-tolerant quantum logic steps. In fact, the resources needed to scale-up fault-tolerant quantum computing hardware are largely set by this task. Tailoring next-generation processors for joint measurements, therefore, could result in improvements to speed, accuracy, or cost—accelerating the development large-scale quantum computers. Here, we motivate such explorations by analyzing an unconventional surface code based on multi… 
1 Citations

Relaxing Hardware Requirements for Surface Code Circuits using Time-dynamics

This work improves on the standard circuit constructions for the surface code, presenting new circuits that can embed on a hexagonal grid instead of a square grid, that can use ISWAP gates instead of CNOT or CZ gates, and that move logical patches around the physical qubit grid while executing.

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