• Corpus ID: 253498982

Hardware optimized parity check gates for superconducting surface codes

  title={Hardware optimized parity check gates for superconducting surface codes},
  author={Matthew Reagor and Thomas C. Bohdanowicz. David Rodriguez Perez and Eyob A. Sete and William J. Zeng},
Error correcting codes use multi-qubit measurements to realize fault-tolerant quantum logic steps. In fact, the resources needed to scale-up fault-tolerant quantum computing hardware are largely set by this task. Tailoring next-generation processors for joint measurements, therefore, could result in improvements to speed, accuracy, or cost—accelerating the development large-scale quantum computers. Here, we motivate such explorations by analyzing an unconventional surface code based on multi… 
1 Citations

Relaxing Hardware Requirements for Surface Code Circuits using Time-dynamics

This work improves on the standard circuit constructions for the surface code, presenting new circuits that can embed on a hexagonal grid instead of a square grid, that can use ISWAP gates instead of CNOT or CZ gates, and that move logical patches around the physical qubit grid while executing.



Realizing repeated quantum error correction in a distance-three surface code.

Quantum computers hold the promise of solving computational problems that are intractable using conventional methods1. For fault-tolerant operation, quantum computers must correct errors occurring

Building a Fault-Tolerant Quantum Computer Using Concatenated Cat Codes

This work presents a comprehensive architectural analysis for a fault-tolerant quantum computer based on cat codes concatenated with outer quantum error-correcting codes, and proposes a system of acoustic resonators coupled to superconducting circuits with a two-dimensional layout.

Repeated quantum error detection in a surface code

In a surface code consisting of four data and three ancilla qubits, repeated error detection is demonstrated and the lifetime and coherence time of the logical qubit are enhanced over those of any of the constituent qubits when no errors are detected.

Entangling logical qubits with lattice surgery

Entanglement between two logical qubits is demonstrated and logical state teleportation between them and the demonstration of these operations—fundamental building blocks for quantum computation—through lattice surgery represents a step towards the efficient realization of fault-tolerant quantum computation.

Logical-qubit operations in an error-detecting surface code

This work realizes a suite of logical operations on a distance-two logical qubit stabilized using repeated error detection cycles, and demonstrates process tomography of logical gates, using the notion of a logical Pauli transfer matrix.

Optimization of the surface code design for Majorana-based qubits

This work provides several qubit layouts that offer favorable trade-offs between qubit overhead, circuit depth and connectivity degree and develops minimized measurement sequences for syndrome extraction, enabling reduced logical error rates and improved fault-tolerance thresholds.

Comparing two-qubit and multiqubit gates within the toric code

In some quantum computing (QC) architectures, entanglement of an arbitrary number of qubits can be generated in a single operation. This property has many potential applications, and may specifically

State preservation by repetitive error detection in a superconducting quantum circuit

The protection of classical states from environmental bit-flip errors is reported and the suppression of these errors with increasing system size is demonstrated, motivating further research into the many challenges associated with building a large-scale superconducting quantum computer.

Realization of arbitrary doubly-controlled quantum phase gates

Developing quantum computers for real-world applications requires understanding theoretical sources of quantum advantage and applying those insights to design more powerful machines. Toward that end,

Qubit parity measurement by parametric driving in circuit QED

This work proposes a hardware-efficient multiqubit parity measurement exploiting the bifurcation dynamics of a parametrically driven nonlinear oscillator and presents analytical and numerical results for two- and four-qubit parity measurements, with high-fidelity readout preserving the parity eigenpaces.