Hardware implementation of montgomery modular multiplication algorithm using iterative architecture

@article{Renardy2015HardwareIO,
  title={Hardware implementation of montgomery modular multiplication algorithm using iterative architecture},
  author={Antonius P. Renardy and Nur Ahmadi and Ashbir A. Fadila and Naufal Shidqi and Trio Adiono},
  journal={2015 International Seminar on Intelligent Technology and Its Applications (ISITIA)},
  year={2015},
  pages={99-102}
}
Modular multiplication is an integral part of RSA cryptosystems and its performance heavily determines the performance of the encryption hardware. This paper provides a hardware implementation of Montgomery's modular multiplication algorithm using iterative architecture. The propsed design is implemented in Verilog HDL and simulated functionally using ModelSim Altera 10.1E. The synthesis is performed using Altera Quartus II 9.1 with target FPGA board Altera DE2-70. The proposed design consumes… CONTINUE READING
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