# Hardware and Software Implementations of RSA Encryption Using Fast Montgomery Modular Multiplication Prof . Kris Gaj George Mason University

@inproceedings{Koontz2006HardwareAS, title={Hardware and Software Implementations of RSA Encryption Using Fast Montgomery Modular Multiplication Prof . Kris Gaj George Mason University}, author={Michael D. Koontz and Ryon Sumner}, year={2006} }

With the heightened emphasis on security in realm of computers and computer networks, the RSA encryption algorithm has seen world-wide use as an effective method to encrypt and protect data. This key-based algorithm relies heavily on integer multiplication to perform the data encryption or decryption, with the speed of the multiplication algorithm contributing heavily to the throughput performance of the RSA encryption algorithm.

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This paper uses carry save adder (CSA) architecture and shows that this architecture has greater performance for FPGA design than other architectures, appropriate for RSA processors based on FPGAs.

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A modular high-speed implementation of the Montgomery Algorithm for the encryption/decryption of data is presented. The circuit is partitioned in well-specified modules in terms of functionality. The…

Fast Montgomery modular multiplication and RSA cryptographic processor architectures

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New, generic silicon architectures for implementing Montgomery's multiplication algorithm are presented and it is shown that using a four-to-two CSA with two extra registers rather than a five- to- two CSA leads to a useful reduction in the critical path of the multiplier, albeit at the expense of a small increase in circuitry.

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This paper proposes an improved (faster) version of the Montgomery multiplication and provides figures about the overhead of these versions relatively to a speed optimised version (theoretically and experimentally).

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Initially developed for fast scalar multiplication on elliptic curves, the scope of Montgomery ladder is extended to any exponentiation in an abelian group, which makes it naturally protected against a large variety of implementation attacks.

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In this paper, an efficient VLSI architecture to compute the n-bit Montgomery modular multiplication is proposed. By using the staged carry save adder (CSA) array, the computation cycles of addition…

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