Hardware-Transactional-Memory Based Speculative Parallel Discrete Event Simulation of Very Fine Grain Models


This article presents an innovative runtime support for speculative parallel processing of discrete event simulation models on multi-core architectures, which exploits Hardware-Transactional-Memory (HTM) facilities for the purpose of state recoverability. In this proposal, the speculative updates on the state of the simulation model are executed as… (More)
DOI: 10.1109/HiPC.2015.45


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