Hardware Support for Prescient Instruction Prefetch

@article{Aamodt2004HardwareSF,
  title={Hardware Support for Prescient Instruction Prefetch},
  author={Tor M. Aamodt and Paul Chow and Per Hammarlund and Hong Wang and John Paul Shen},
  journal={10th International Symposium on High Performance Computer Architecture (HPCA'04)},
  year={2004},
  pages={84-84}
}
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch — an approach to improving single-threaded application performance by using helper threads to perform instruction prefetch. We demonstrate the need for enabling store-to-load communication and selective instruction execution when directly pre-executing future regions of an application that suffer I-cache misses. Two novel hardware mechanisms, safe-store and YAT-bits, are introduced that help… CONTINUE READING

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Key Quantitative Results

  • On a research Itanium®SMT processor with next line and streaming I-prefetch mechanisms that incurs latencies representative of next generation processors, prescient instruction prefetch can improve performance by an average of 10.0% to 22% on a set of SPEC 2000 benchmarks that suffer significant I-cache misses.

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