Hardware Speedups in Long Integer Multiplication

@inproceedings{Shand1990HardwareSI,
  title={Hardware Speedups in Long Integer Multiplication},
  author={Mark Shand and Patrice Bertin and Jean Vuillemin},
  booktitle={SPAA},
  year={1990}
}
We present various experiments in Hardware/Software design tradeoffs met in speeding up long integer multiplications. This work spans over a year, with more than 12 different hardware designs tested and measured.To implement these designs, we rely on our PAM (for Programmable Active Memory, see [BRV]) technology which provides us with a 50 millisecond turn-around time silicon foundry for implementing up to 50K gate logic designs fully equipped with fast local RAM and host bus interface.First… CONTINUE READING

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