Hardware Implementation of Fano Decoder for Polarization-Adjusted Convolutional (PAC) Codes

  title={Hardware Implementation of Fano Decoder for Polarization-Adjusted Convolutional (PAC) Codes},
  author={Amir Mozammel},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  • Amir Mozammel
  • Published 19 November 2020
  • Computer Science
  • IEEE Transactions on Circuits and Systems II: Express Briefs
This brief proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture uses a novel branch metric unit specific to PAC codes. The proposed decoder is tested on FPGA, and its performance is evaluated on ASIC using TSMC 28 nm 0.72 V library. The decoder can be clocked at 500 MHz and reach an average information throughput of 38 Mb/s at 3.5 dB signal-to-noise ratio for a block length of 128 and a code rate of 1/2. 

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