Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts

@inproceedings{Olson2000HardwareIO,
  title={Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts},
  author={Dan Olson and K. Wayne Current},
  booktitle={ISMVL},
  year={2000}
}
A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrates several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results are presented and discussed. 1.0: Introduction After a brief review of the Supplementary Symmetrical… CONTINUE READING

References

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The Supplementary Symmetrical Logic Circuit Structure (SUS-LOCTM)

Edgar D. Olson
Patent pending, • 1998
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