Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders


By optimizing the number of look-ahead steps of the first layer of the previous low-latency architectures for M-step look-ahead high-throughput rate Viterbi decoders, this paper improves the hardware efficiency by large percentage with slight increase or even further decrease of the latency for the add-compare-select (ACS) computation. This is true… (More)
DOI: 10.1109/TCSII.2008.2008061

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