• Corpus ID: 239009858

Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes

@article{Zhang2021HardwareAO,
  title={Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes},
  author={Peng W. Zhang and Francis Chung-Ming Lau and Chiu-Wing Sham},
  journal={ArXiv},
  year={2021},
  volume={abs/2110.07906}
}
Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimateShannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a… 
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