Hardware Accelerator for Probabilistic Inference in 65-nm CMOS

Abstract

A hardware accelerator is presented to compute the probabilistic inference for a Bayesian network (BN) in distributed sensing applications. For energy efficiency, the accelerator is operated at a near-threshold voltage of 0.5 V, while achieving a maximum clock frequency of 33 MHz. Clique-tree message passing algorithm is leveraged to compute the probabilistic inference. The theoretical maximum size of a factor that the proposed hardware accelerator can handle is 2(8×20)=160 entries, which is sufficient for handling massive BNs, such as PATHFINDER, MUNIN, and so on (>1000 nodes). A Logical Alarm Reduction Mechanism (ALARM) BN is used to benchmark the performance of the accelerator. The accelerator consumes 76 nJ to execute the ALARM network using a clique-tree message-passing algorithm, while the same algorithm executed on an ultralow-power microcontroller consumes 20 mJ.

DOI: 10.1109/TVLSI.2015.2420663

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Cite this paper

@article{Khan2016HardwareAF, title={Hardware Accelerator for Probabilistic Inference in 65-nm CMOS}, author={Osama Ullah Khan and David D. Wentzloff}, journal={IEEE Trans. VLSI Syst.}, year={2016}, volume={24}, pages={837-845} }