HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder

@inproceedings{Verderber2003HWSWPO,
  title={HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder},
  author={Matjaz Verderber and Andrej Zemva and Damjan Lampret},
  booktitle={DATE},
  year={2003}
}
In this paper, we propose an optimized real-time MPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We made time/power-consumption analysis and optimization of the MPEG-2 decoder. On the basis of the achieved results, we decided for HW implementation of the IDCT and VLD algorithms. Remaining parts were realized in SW with 32-bit RISC processor. MPEG-2 decoder (RISC processor, IDCT core, VLD core) has been described in Verilog/VHDL and… CONTINUE READING

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