Corpus ID: 42620778

HIGH-SPEED FREQUENCY MULTIPLIER DESIGN FOR DUAL EDGE DETECTOR BASED DLL-CLOCK GENERATOR

@inproceedings{Ramya2017HIGHSPEEDFM,
  title={HIGH-SPEED FREQUENCY MULTIPLIER DESIGN FOR DUAL EDGE DETECTOR BASED DLL-CLOCK GENERATOR},
  author={V. Ramya and M. Vasanthakumar},
  year={2017}
}
The aim of delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. By applying the logic to the pulse generator and multiplication-ratio control logic design, the frequency of the delay is determined. Finally, a numerical analysis is performed by means of the following frequency multipliers. The… Expand

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