HDL-based modeling of embedded processor behavior for retargetable compilation
@inproceedings{Laupers1998HDLbasedMO, title={HDL-based modeling of embedded processor behavior for retargetable compilation}, author={Rainer Laupers}, year={1998} }
The concept of retargetability enables compiler technology to keep pace with the increasing variety of domain-specific embedded processors. In order to achieve user retargetability, powerful processor modeling formalisms are required. Most of the recent modeling formalisms concentrate on horizontal, VLIW-like instruction formats. However, for encoded instruction formats with restricted instruction-level parallelism (ILP), a large number of ILP constraints might need to be specified, resulting… CONTINUE READING
Topics from this paper
7 Citations
Processor/memory co-exploration on multiple abstraction levels
- Computer Science
- 2003 Design, Automation and Test in Europe Conference and Exhibition
- 2003
- 25
- PDF
Automatic software toolkit generation for embedded systems-on-chip
- Computer Science
- ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)
- 1999
- 19
Retargetable generation of TLM bus interfaces for MP-SoC platforms
- Computer Science
- 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05)
- 2005
- 9
- PDF
A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms
- Computer Science
- Proceedings Design, Automation and Test in Europe Conference and Exhibition
- 2004
- 73
- PDF
Software Performance Estimation in MPSoC Design
- Computer Science
- 2007 Asia and South Pacific Design Automation Conference
- 2007
- 28
- PDF
References
SHOWING 1-10 OF 15 REFERENCES
Describing instruction set processors using nML
- Computer Science
- Proceedings the European Design and Test Conference. ED&TC 1995
- 1995
- 304
- PDF
A graph based processor model for retargetable code generation
- Computer Science
- Proceedings ED&TC European Design and Test Conference
- 1996
- 41
- PDF
Instruction-set matching and selection for DSP and ASIP code generation
- Computer Science
- Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC
- 1994
- 163
A BDD-based frontend for retargetable compilers
- Computer Science
- Proceedings the European Design and Test Conference. ED&TC 1995
- 1995
- 34
- PDF
Translating Signal Flowcharts into Microcode for Custom Digital Signal Processors
- Computer Science
- 1993
- 15
- PDF
An integrated approach to retargetable code generation
- Computer Science
- Proceedings of 7th International Symposium on High-Level Synthesis
- 1994
- 56
- PDF
Generation of software tools from processor descriptions for hardware/software codesign
- Computer Science
- DAC
- 1997
- 61
- PDF
Instruction selection using binate covering for code size optimization
- Computer Science
- Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)
- 1995
- 55
Automatic instruction code generation based on trellis diagrams
- Computer Science
- [Proceedings] 1992 IEEE International Symposium on Circuits and Systems
- 1992
- 40