HARP: hard-wired routing pattern FPGAs

Abstract

Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such great flexibility comes at a high cost in terms of area, delay and power. We propose a new FPGA routing architecture\footnoteThis work was supported in part by a grant from NSF under contract CAREER CCF-0347891 that utilizes a mixture of hardwired and traditional flexible switches. The result is 24% reduction in leakage power consumption, 7% smaller area and 24% shorter delays, which translates to 30% increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is %, including dynamic power, reduced by 8%.

DOI: 10.1145/1046192.1046196

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Cite this paper

@inproceedings{Sivaswamy2005HARPHR, title={HARP: hard-wired routing pattern FPGAs}, author={Satish Sivaswamy and Gang Wang and Cristinel Ababei and Kia Bazargan and Ryan Kastner and Elaheh Bozorgzadeh}, booktitle={FPGA}, year={2005} }