Design and chip implementation of an instruction scheduling free ubiquitous processor
Parallelism is one of fundamental concepts of recent years’ trend in developing cutting edge VLSI processors in order to achieve power conscious high performance. HCgorilla is a ubiquitous processor that does not make much of high clock speed, but seeks high performance by applying the architecture of multicore and multiple pipeline. Each of two symmetric cores is composed of Java compatible media pipes and cipher pipes for cipher streaming. Similarly to other processors, HCgorilla is also accompanied with the awkward issue of instruction pipelining. Focusing on this, this paper shows how H/S collaborative parallelism can be used to accelerate the processing speed of the HCgorilla. The novelty of utilizing media pipes as fully as possible owes to a triple scheme for a waved MFU (multifunctional unit), multistack, and interleaved issue of related codes. Since this is useful for out-of-order arithmetic issue in conjunction with parallel stack operation, the triple scheme achieves a processor system free from not only instruction scheduling but also pipeline disturbance. The triple scheme is applied for the improved version of an HCgorilla chip and parallelizing compilers. According to H/S collaboration, these parallelizing steps are moved to web servers. This surely lightens the burden of mobile platforms.