Guest Editorial: Emerging Technologies and Architectures for Manycore Computing Part 1: Hardware Techniques

@article{Beux2018GuestEE,
  title={Guest Editorial: Emerging Technologies and Architectures for Manycore Computing Part 1: Hardware Techniques},
  author={S{\'e}bastien Le Beux and Pauline Gratz and Ian O’Connor},
  journal={IEEE Trans. Multi Scale Comput. Syst.},
  year={2018},
  volume={4},
  pages={97-98}
}
THE pursuit ofMoore’s Law is slowing and the exploration of alternative devices is underway to replace the CMOS transistor and traditional architectures at the heart of data processing.Moreover, the emergence of stringent application constraints, particularly those linked to energy consumption, require new system architectural strategies (e.g. manycore) and real-time operational adaptability approaches. Such complex systems require new and powerful design and programmingmethods to ensure… 

International Journal of Reconfigurable and Embedded Systems (IJRES)

TLDR
This paper presents a cost and performance efficient multi-level cache system with per core L1 and last level shared bus cache on each bus line of a costefficient geometrically bus-based interconnection for moderate number of cores.

Cost-efficient reconfigurable geometrical bus interconnection system for many-core platforms

  • T. RameshK. Abed
  • Computer Science
    International Journal of Reconfigurable and Embedded Systems (IJRES)
  • 2021
TLDR
This paper proposes a cost efficient generalized reconfigurable bus-based interconnection for many-core system with reduced number of bus connections and presents four geometrical interconnect configurations that provide reduced cost per bandwidth and can achieve higher system throughput with bus cache.