GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks

@article{Nai2017GraphPIMEI,
  title={GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks},
  author={Lifeng Nai and Ramyad Hadidi and Jaewoong Sim and Hyojong Kim and Pranith Kumar and Hyesoon Kim},
  journal={2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)},
  year={2017},
  pages={457-468}
}
  • L. Nai, Ramyad Hadidi, Hyesoon Kim
  • Published 1 February 2017
  • Computer Science
  • 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
With the emergence of data science, graph computing has become increasingly important these days. Unfortunately, graph computing typically suffers from poor performance when mapped to modern computing systems because of the overhead of executing atomic operations and inefficient utilization of the memory subsystem. Meanwhile, emerging technologies, such as Hybrid Memory Cube (HMC), enable the processing-in-memory (PIM) functionality with offloading operations at an instruction level… 
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170 Citations
Highly Influential Citations
19
Background Citations
93
Methods Citations
47
Results Citations
6

170 Citations

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Citation Type

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TLDR
CoPIM is presented, a novel PIM workload offloading architecture that can dynamically determine which portion of the graph workload can benefit more from PIM-side computation and reduces the size of offloading instructions and also improves the overall performance with less energy consumption.
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TLDR
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GraphH, a PIM architecture for graph processing on the hybrid memory cube array, is proposed to tackle all four problems mentioned above, including random access pattern causing local bandwidth degradation, poor locality leading to unpredictable global data access, heavy conflicts on updating the same vertex, and unbalanced workloads across processing units.
Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads
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An in-depth data-type-aware characterization of graph processing workloads on a simulated multi-core architecture finds that the load-load dependency chains involving different application data types form the primary bottleneck in achieving a high memory-level parallelism.
Heterogeneous Memory Subsystem for Natural Graph Analytics
TLDR
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A Heterogeneous PIM Hardware-Software Co-Design for Energy-Efficient Graph Processing
TLDR
There is no absolute winner between these two representative PIM technologies for graph applications, which often exhibit irregular workloads, and a new heterogeneous PIM hardware, called Hetraph, is introduced to facilitate energy-efficient graph processing.
LCCG: a locality-centric hardware accelerator for high throughput of concurrent graph processing
TLDR
This paper proposes LCCG, a Locality-Centric programmable accelerator that augments the many-core processor for achieving higher throughput of Concurrent Graph processing jobs and develops a novel topology-aware execution approach into the accelerator design to regularize the graph traversals for multiple jobs on-the-fly according to the graph topology.
Energy characterization of graph workloads
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Two high- level compiler optimizations, i.e., loop fusion and edge flipping, and one low-level compiler transformation leveraging hardware support for remote atomic updates to address overheads arising from thread migration, creation, synchronization, and atomic operations are explored.
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