Global Real-Time Memory-Centric Scheduling for Multicore Systems

Abstract

As the number of cores increases, more master components can simultaneously access main memory. In realtime systems, this ongoing trend is leading to crippling pessimism when computing the worst-case cache miss time, since a memory request could potentially contend with other requests coming from every other core in the system. CPU-centric scheduling policies, therefore, are no longer sufficient to guarantee schedulability without introducing unacceptable pessimism for memoryintensive task sets. For this reason, we believe a shift is needed towards real-time scheduling approaches that can prevent timing interference from memory contention, while still making efficient use of the multicore platform. Previously, we have demonstrated the practicality of the PREM task model, where each job consists of a sequence of phases, some of which access memory and some of which perform only computation on cached data. In this work, we present the first global memory-centric scheduling policy for memoryintensive task sets whose jobs can be modeled as a sequence of memory-intensive (memory phase) and execution-intensive (execution phase) phases. The proposed policy is parameterizable based on the number of cores which are allowed to concurrently access main memory without saturating it. Building upon results from multicore response-time analysis, we introduce the notion of virtual memory cores as a fundamental technique for performing phase-based response time analysis for memory-intensive task sets. Finally, we use synthetic task set generation to demonstrate that proposed scheduling policy and related schedulability bound do indeed better schedule memory-intensive task sets when compared to state-of-art multicore scheduling.

DOI: 10.1109/TC.2015.2500572

Extracted Key Phrases

7 Figures and Tables

Cite this paper

@article{Yao2016GlobalRM, title={Global Real-Time Memory-Centric Scheduling for Multicore Systems}, author={Gang Yao and Rodolfo Pellizzoni and Stanley Bak and Heechul Yun and Marco Caccamo}, journal={IEEE Trans. Computers}, year={2016}, volume={65}, pages={2739-2751} }