• Corpus ID: 1758996

Global Placement Techniques for VLSI Physical Design Automation

  title={Global Placement Techniques for VLSI Physical Design Automation},
  author={Zhen Yang and Shawki Areibi},
VLSI physical design automation plays a vital role as we move to deep sub-micron designs below 0.18 microns. Power dissipation, performance and area are dominated by interconnections between elements in the circuit under consideration. Global Placement followed by iterative improvement placement (detailed placement) is the most robust, simple and successful approach in solving the placement problem. Initial solution produced by global placement will largely influence the convergence of the… 

An Analogous Computation on Hybrid Genetic Algorithm for VLSI Physical design Specific to Placement Problem

Due to rapid advances in VLSI design technology during the last decade, the complexity and size of circuits have been rapidly increasing, placing a demand on industry for faster and more efficient

Multithreaded Memetic Algorithm for VLSI Placement Problem

A novel memetic algorithm, which is used to solve standard cell placement problem is presented, and hybrid, knowledge based techniques, which support the algorithm during the creation of the initial individuals and the optimization process are applied.

Area/Congestion-Driven Placement for VLSI Circuit Layout

A new hierarchal clustering heuristic is presented which clusters a standard-cell circuit by greedily collapsing net hyperedges by size, but not permitting very large clusters from forming, demonstrating excellent characteristics for reducing the execution time of standard- cell placement while achieving better results compared to non-clustered circuit placement and placement using other edge-based clustering methods.

Best Response Dynamics for VLSI Physical Design Placement

  • M. RapoportTami Tamir
  • Computer Science
    2019 Federated Conference on Computer Science and Information Systems (FedCSIS)
  • 2019
The results show that selfish local-search, especially when applied with cooperatives of components, may be beneficial for the placement problem, and suggest several BRD methods, based on selfish migrations of a single or a cooperative of components.

Effective Memetic Algorithms for VLSI Design = Genetic Algorithms Local Search Multi-Level Clustering

Results obtained indicate that Memetic Algorithms based on local search, clustering and good initial solutions improve solution quality on average by 35 for the VLSI circuit partitioning problem and 54 for theVLSI standard cell placement problem.

On the application of iterative solvers to KKT systems in Interior Point methods for Large-Scale Quadratic Programming problems

The aim of the research activity described in this thesis has been the analysis, the development and the implementation of iterative methods for the efficient solution of the KKT systems arising at each iteration of Interior Point methods for large-scale convex Quadratic Programming problems.

Parameterized algorithmics for linear arrangement problems

  • H. Fernau
  • Computer Science, Mathematics
    Discret. Appl. Math.
  • 2008

A Comparison of Heuristics for FPGA Placement

This paper presents several constructive and iterative improvement placement based heuristics that significantly reduce the amount of computation time required to achieve high-quality placements, compared with VPR.



Cell placement using constructive and iterative improvement methods

Modem integrated circuits contain thousit~lds of switching c& making their design an overwbelming task. The design procedure is t h d o r e divided into sequence of design steps. Circuit layout is

Genetic algorithms for VLSI design, layout & test automation

This book provides details about some of the EDA applications where GAs have been used, including partitioning, automatic placement and routing, technology mapping for FPGAs, automatic test generation, and power estimation.

A new approach to effective circuit clustering

  • L. HagenA. Kahng
  • Computer Science
    1992 IEEE/ACM International Conference on Computer-Aided Design
  • 1992
The DS quality measure, a general metric for evaluation of clustering algorithms, is established and motivates the RW-ST algorithm, a self-tuning clustering method based on random walks in the circuit netlist, which efficiently captures a globally good circuit clustering.

Efficient and effective placement for very large circuits

  • Wern-Jieh SunC. Sechen
  • Computer Science
    Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
  • 1993
A new hierarchical annealing-based placement program which yields total wire length reductions of up to 9% while consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6.0.

Near-optimal quadratic-based placement for a class of IC layout problems

  • J. Blanks
  • Computer Science
    IEEE Circuits and Devices Magazine
  • 1985
Both the experimental and theoretical results indicate an asymptotic approach to optimality with large problem sizes in IC layout algorithms.

Clustering and linear placement

Two algorithms are presented, one for clustering a set of interconnected nodes and the other for forming a linear placement of clustered interconnected nodes, designed to analyze the structure of digital logic for automatic placement of logic functions on a MOS/LSI chip.

Automatic Placement A Review of Current Techniques

This review provides an overview of the placement function within automatic layout systems and divides placement algorithms into two classes: constructive and iterative.

Recent directions in netlist partitioning: a survey

Multilevel Hypergraph Partitioning: Application In Vlsi Domain

The experiments show that the multilevel hypergraph partitioning algorithm produces high quality partitioning in relatively small amount of time and outperforms other schemes (in hyperedge cut) quite consistently with larger margins.

Attractor-repeller approach for global placement

  • H. EtawilS. AreibiA. Vannelli
  • Computer Science
    1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)
  • 1999
This work added new attractive and repulsive forces to the traditional formulation of analytic placement so that overlap among cells is diminished without repartitioning the placement area.