Global Multi-Threaded Instruction Scheduling


Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utiliz- ing the increasing transistor counts in the face of physi- cal and micro-architectural limitations. Despite this move, CMPs do not directly improve the performance of single- threaded codes, a characteristic of most applications. In or- der to… (More)
DOI: 10.1109/MICRO.2007.17


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@article{Ottoni2007GlobalMI, title={Global Multi-Threaded Instruction Scheduling}, author={Guilherme Ottoni and David I. August}, journal={40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)}, year={2007}, pages={56-68} }