Corpus ID: 13309360

Genetic Algorithm Optimization for Coefficient of FFT Processor

  title={Genetic Algorithm Optimization for Coefficient of FFT Processor},
  author={Pang Jia Hong and Nasri B. Sulaiman},
This paper describes the implementation of Single-objective Genetic Algorithm (SOGA) and Multi-objectives Genetic Algorithm (MOGA) to optimize the pipelined Fast Fourier Transform (FFT) coefficient in order to improve the performance of Signal to Noise Ratio (SNR) and also the Switching Activity (SA). The SA and SNR are optimized separately in a Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor using SOGA. The MOGA optimized both objectives using… Expand
Multi-Objective Genetic Algorithms for computing Fast Fourier Transform for evolving Smart Sensors devices using Field Programmable gate arrays
A multi- objective genetic algorithm for computing Fast Fourier Transform for evolving smart sensor devices has been designed and simulated in software in a field programmable gateway array using Altera Quartus II 13.0 to show significant improvements in all performance measures. Expand
Instruction Set Extension Through Partial Customization Of Low-End Risc Processor
This paper covers the design technique of an enhanced Reduce Instruction Set Computer (RISC)-based processor core using application-specific instruction-set processor (ASIP) methodology. TheExpand


A genetic algorithm for the optimisation of a reconfigurable pipelined FFT processor
  • N. Sulaiman, T. Arslan
  • Computer Science
  • Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004.
  • 2004
Two forms of optimisation; input data optimisation and FFT coefficients optimisation are investigated in this paper and the word length is optimised down to 10 bits for input data and 8 bits for the FFT coefficient. Expand
A Multi-Objective Genetic Algorithm for On-Chip Real-time Adaptation of a Multi-Carrier Based Telecommunications Receiver
  • N. Sulaiman, A. Erdogan
  • Computer Science
  • First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)
  • 2006
A specially tailored genetic algorithm is developed in order to adapt the complete receiver while dynamically optimizing the critical fast Fourier transform section of the receiver for both error value and power consumption. Expand
Word-length optimization of a pipelined FFT processor
  • J. He, J. Wang, X. Xu
  • Computer Science
  • 2011 International Conference on Consumer Electronics, Communications and Networks (CECNet)
  • 2011
Three Matlab models for the processor are developed in which the internal data are formatted as floating point, fixed point and hybrid floating point respectively, and simulations show that hybrid floating Point can achieve better and constant performance compared to fixed point with progressive word-length in term of SQNR and memory size. Expand
Multi-objective design strategy for high-level low power design of DSP systems
  • M. Bright, T. Arslan
  • Engineering, Computer Science
  • ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)
  • 1999
This paper presents a methodology for effective optimisation of VLSI based DSP designs in a multi-objective CAD framework that uses a stochastic search technique, based on a genetic algorithm, to determine power optimal designs with minimum area implementation. Expand
A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications
This paper proposes a technique to reduce the power consumption of a popular low power radix-4 pipelined FFT processor by modifying its operation sequence using a novel commutator architecture. Expand
Wordlength optimization of a pipelined FFT processor
This paper describes the optimization of the word lengths in an 8 k-points pipelined FFT processor. The word lengths can be freely chosen since the FFT is implemented as a full custom ASIC. AccordingExpand
A genetic algorithm for multiple fault model test generation for combinational VLSI circuits
The authors present a genetic algorithm (GA) for the automatic generation of test vector-pairs for the detection of both delay and single stuck-at-fault models in combinational digital VLSI circuits.Expand
Monreale: a new genetic algorithm for the solution of the channel routing problem
A novel channel router algorithm (Monreale) is implemented which is based on a modified genetic algorithm (GA) with a well balanced combination of the fast performance characterizing the steepest descent method and of the high level of parallelism and of local minimum trapping avoidanceCharacterizing the GA approach. Expand
Architectural evaluation of flexible digital signal processing for wireless receivers
  • N. Zhang, R. Brodersen
  • Computer Science
  • Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)
  • 2000
This approach to using function-specific architectures to provide sufficient flexibility identified at system level that have low energy consumption overhead is evaluated and energy efficiency and computation density are compared to other reconfigurable architectures based on different configuration granularities. Expand
Co-Emulation Design for OFDM Baseband Transceiver
This paper uses Top-down method to design WLAN802.11a based Orthogonal Frequency Division Multiplexing (OFDM) Baseband Transceivers and exploits Verilog hardware description language to complete the design of Convolutional encoder/Viterbi decoder, Mapper/Demapper and FFT/IFFT which all meet the timing pulse specifications of WLAN11a. Expand