Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

Abstract

A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology. A key feature is that it achieves a low packet propagation latency of… (More)
DOI: 10.1109/FPL.2011.25

Topics

12 Figures and Tables

Statistics

051015201520162017
Citations per Year

Citation Velocity: 7

Averaging 7 citations per year over the last 3 years.

Learn more about how we calculate this metric in our FAQ.

Slides referencing similar topics